Launched in 2004, dmesgd aims to provide a user-submitted repository of searchable *BSD dmesgs. The dmesg(8) command displays the system message buffer's content, and during boot a copy is saved to /var/run/dmesg.boot. This buffer contains the operating system release, name and version, a list of devices identified, plus a whole host of other useful information. We hope others find this resource useful and further contribute to its growth. Contact us at [ admin at lists dot nycbug dot org ]. Note that this site is not a substitute for sending the dmesg directly to the respective project.
Date: 2017-02-10 08:19:33
From: Sevan / Venture37
Description: HP T5325 thinkclient (kirkwood SoC) (mvpex, pci and pchb drivers disabled due to malloc size bug)
## Booting image at 00800000 ...
Image Name: NetBSD/hpt5325 7.99.59
Created: 2017-02-10 8:06:39 UTC
Image Type: ARM NetBSD Kernel Image (uncompressed)
Data Size: 5541460 Bytes = 5.3 MB
Load Address: 00008000
Entry Point: 00008000
Verifying Checksum ... OK
OK
## Transferring control to NetBSD stage-2 loader (at address 00008000) ...
NetBSD/evbarm (hpt5325) booting ...
[ Kernel symbol table missing! ]
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
NetBSD 7.99.59 (HPT5325) #2: Fri Feb 10 08:05:58 GMT 2017
xxx@xxx:/netbsd-src-ro/usr/src/sys/arch/evbarm/compile/HPT5325
total memory = 512 MB
avail memory = 496 MB
sysctl_createv: sysctl_create(machine_arch) returned 17
mainbus0 (root)
cpu0 at mainbus0 core 0: Sheeva 88SV131 rev 1 (ARM9E-S V5TE core)
cpu0: DC enabled IC enabled WB enabled EABT branch prediction enabled
cpu0: 16KB/32B 4-way L1 VIVT Instruction cache
cpu0: 16KB/32B 4-way write-back-locking-C L1 VIVT Data cache
mvsoc0 at mainbus0: Marvell 88F6281 Rev. A1 Kirkwood
mvsoc0: CPU Clock 1200.000 MHz SysClock 400.000 MHz TClock 200.000 MHz
mvsoctmr0 at mvsoc0 unit 0 offset 0x20300-0x203ff irq 65: Marvell SoC Timer
mvsocgpp at mvsoc0 unit 0 not configured
mvsocrtc0 at mvsoc0 unit 0 offset 0x10300-0x10317: Marvell SoC Real Time Clock
com0 at mvsoc0 unit 0 offset 0x12000-0x1201f irq 33: ns16550a, working fifo
com0: console
com1 at mvsoc0 unit 1 offset 0x12100-0x1211f irq 34: ns16550a, working fifo
ehci0 at mvsoc0 unit 0 offset 0x50000-0x50fff irq 19: Marvell USB 2.0 Interface
usb0 at ehci0: USB revision 2.0
gtidmac at mvsoc0 unit 0 not configured
gttwsi0 at mvsoc0 unit 0 offset 0x11000-0x110ff irq 29: Marvell TWSI controller
iic0 at gttwsi0: I2C bus
mvcesa at mvsoc0 unit 0 not configured
mvgbec0 at mvsoc0 unit 0 offset 0x70000-0x73fff: Marvell Gigabit Ethernet Controller
mvgbe0 at mvgbec0 port 0 irq 11
mvgbe0: Ethernet address f4:ce:46:
ukphy0 at mvgbe0 phy 8: OUI 0x000ac2, model 0x0022, rev. 0
ukphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
mvgbec1 at mvsoc0 unit 1 offset 0x74000-0x77fff: Marvell Gigabit Ethernet Controller
mvgbe at mvgbec1 port 0 not configured
mvpex at mvsoc0 unit 0 not configured
mvsata0 at mvsoc0 unit 0 offset 0x80000-0x87fff irq 21: Marvell Serial-ATA Host Controller (SATAHC)
mvsata0: GenIIe, 1hc, 2port/hc
atabus0 at mvsata0 channel 0
atabus1 at mvsata0 channel 1
mvsdio at mvsoc0 unit 0 not configured
uhub0 at usb0: Marvell EHCI root hub, class 9/0, rev 2.00/1.00, addr 1
mvsata0 port 0: device present, speed: 3.0Gb/s
wd0 at atabus0 drive 0
wd0: <SM224>
wd0: 463 MB, 942 cyl, 16 head, 63 sec, 512 bytes/sect x 949536 sectors
uhub1 at uhub0 port 1: SMSC USB 2.0 4-Port Hub, class 9/0, rev 2.00/0.00, addr 2
uhub1: multiple transaction translators
umass0 at uhub1 port 4 configuration 1 interface 0
umass0: Generic Mass Storage, rev 2.00/1.09, addr 3
scsibus0 at umass0: 2 targets, 1 lun per target
sd0 at scsibus0 target 0 lun 0: <Generic, Flash Disk, 8.07> disk removable
sd0: fabricating a geometry
sd0: 1921 MB, 1921 cyl, 64 head, 32 sec, 512 bytes/sect x 3934208 sectors
boot device: <unknown>