Launched in 2004, dmesgd aims to provide a user-submitted repository of searchable *BSD dmesgs. The dmesg(8) command displays the system message buffer's content, and during boot a copy is saved to /var/run/dmesg.boot. This buffer contains the operating system release, name and version, a list of devices identified, plus a whole host of other useful information. We hope others find this resource useful and further contribute to its growth. Submit your dmesg today.


Date: 2017-03-10 04:31:20
From: Sevan / Venture37
Description: BeagleBone Black, Rev A5c
reading netbsd-beaglebone.ub
3985108 bytes read in 222 ms (17.1 MiB/s)
U-Boot# bootm 82000000
## Booting kernel from Legacy Image at 82000000 ...
   Image Name:   NetBSD/beagle 7.99.65
   Created:      2017-03-09  13:30:25 UTC
   Image Type:   ARM NetBSD Kernel Image (uncompressed)
   Data Size:    3985044 Bytes = 3.8 MiB
   Load Address: 80300000
   Entry Point:  80300000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK
## Transferring control to NetBSD stage-2 loader (at address 80300000) ...

uboot arg = 0x9e730fb0, 0, 0x9f7a0af1, 0x9f7a0af1
[ Kernel symbol table missing! ]
Loaded initial symtab at 0x8065ee2c, strtab at 0x80695c4c, # entries 13225
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
    2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017
    The NetBSD Foundation, Inc.  All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
    The Regents of the University of California.  All rights reserved.

NetBSD 7.99.65 (BEAGLEBONE.201703091100Z)
total memory = 512 MB
avail memory = 500 MB
sysctl_createv: sysctl_create(machine_arch) returned 17
timecounter: Timecounters tick every 10.000 msec
mainbus0 (root)
cpu0 at mainbus0 core 0: 1000 MHz Cortex-A8 r3p2 (Cortex V7A core)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB/64B 4-way L1 VIPT Instruction cache
cpu0: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
cpu0: 256KB/64B 8-way write-through L2 PIPT Unified cache
vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
obio0 at mainbus0 base 0x44c00000-0x44ffffff: On-Board IO
prcm0 at obio0 addr 0x44e00000-0x44e01fff: Power, Reset and Clock Management
sitaracm0 at obio0 addr 0x44e10000-0x44e11fff: control module, rev 1.0
sitaracm0: AM3359 Silicon Revision 2.0: 0x20ff0383<ICSS,CPSW,DCAN,ICSS_FEA EtherCAT functionality=0x0=disabled,ICSS_FEA TX_AUTO_SEQUENCE=0x0=disabled>
obio1 at mainbus0 base 0x48000000-0x48ffffff: On-Board IO
omapicu0 at obio1 addr 0x48200000-0x48200fff intrbase 0
omapgpio1 at obio1 addr 0x4804c000-0x4804cfff
gpio1 at omapgpio1: 32 pins
omapgpio2 at obio1 addr 0x481ac000-0x481acfff
gpio2 at omapgpio2: 32 pins
omapgpio3 at obio1 addr 0x481ae000-0x481aefff
gpio3 at omapgpio3: 32 pins
obio2 at mainbus0 base 0x4a000000-0x4affffff: On-Board IO
gpmc0 at mainbus0 base 0x50000000: General Purpose Memory Controller, rev 6.0
gpmc0: CS#0 valid, addr 0x00000000, size  16MB
edma0 at mainbus0 base 0x49000000-0x490fffff
tiotg0 at mainbus0 base 0x47400000-0x47404fff: TI dual-port USB controller: version v1.0.0.13
motg0 at tiotg0 port 0: 0x4ea20800 version v0.0.0
motg0: Dynamic FIFO sizing detected, assuming 16Kbytes of FIFO RAM
usb0 at motg0: USB revision 2.0
motg1 at tiotg0 port 1: 0x4ea20800 version v0.0.0
motg1: Dynamic FIFO sizing detected, assuming 16Kbytes of FIFO RAM
usb1 at motg1: USB revision 2.0
com0 at obio0 addr 0x44e09000-0x44e09fff intr 72: OMAP UART, working fifo
com0: console
omapgpio0 at obio0 addr 0x44e07000-0x44e07fff
gpio0 at omapgpio0: 32 pins
tiiic0 at obio0 addr 0x44e0b000-0x44e0bfff intr 70: rev 0.11, scheme 1
tiiic0: 32-bytes FIFO
iic0 at tiiic0: I2C bus
seeprom0 at iic0 addr 0x50: AT24Cxx or compatible EEPROM: size 32768
tps65217pmic0 at iic0 addr 0x24: TPS65217C Power Management Multi-Channel IC (rev 1.2)
tps65217pmic0: power sources [USB] max 1800 mA, AC max 2500 mA
tps65217pmic0: [LDO1: 1800 mV] [LDO2: 3300 mV] [LDO3: 1800 mV] [LDO4: 3300 mV] [DCDC1: 1500 mV] [DCDC2: 1325 mV] [DCDC3: 1125 mV] 
omapdmtimer1 at obio0 addr 0x44e31000-0x44e31fff intr 67: DMTIMER1ms
omapwdt32k0 at obio0 addr 0x44e35000-0x44e35fff: rev 0.1
sdhc0 at obio1 addr 0x48060000-0x48060fff intr 64: SDHC controller
sdhc0: EDMA tx channel 24, rx channel 25
sdhc0: SDHC 2.0, rev 49, platform DMA, 96000 kHz, HS 1.8V 3.0V, 1024 byte blocks
sdmmc0 at sdhc0 slot 0
sdhc1 at obio1 addr 0x481d8000-0x481d8fff intr 28: SDHC controller
sdhc1: EDMA tx channel 2, rx channel 3
sdhc1: SDHC 2.0, rev 49, platform DMA, 96000 kHz, HS 1.8V 3.0V, 1024 byte blocks
sdmmc1 at sdhc1 slot 0
omapdmtimer0 at obio1 addr 0x48040000-0x48040fff intr 68: DMTIMER2
omapdmtimer2 at obio1 addr 0x48044000-0x48044fff intr 92: DMTIMER4
trng0 at obio1 addr 0x48310000-0x48311fff intr 111
cpsw0 at obio2 addr 0x4a100000-0x4a107fff intrbase 40: TI Layer 2 3-Port Switch
cpsw0: Ethernet address c8:a0:30:
ukphy0 at cpsw0 phy 0: OUI 0x00800f, model 0x000f, rev. 1
ukphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
timecounter: Timecounter "clockinterrupt" frequency 100 Hz quality 0
timecounter: Timecounter "dmtimer" frequency 24000000 Hz quality 100
uhub0 at usb0: Mentor Graphics MOTG root hub, class 9/0, rev 2.00/1.00, addr 1
uhub0: 1 port with 1 removable, self powered
uhub1 at usb1: Mentor Graphics MOTG root hub, class 9/0, rev 2.00/1.00, addr 1
uhub1: 1 port with 1 removable, self powered
ld1 at sdmmc1: <0xfe:0x014e:MMC02G:0x00:0x26ca609b:0x000>
ld1: 1832 MB, 930 cyl, 64 head, 63 sec, 512 bytes/sect x 3751936 sectors
ld0 at sdmmc0: <0x02:0x544d:SA16G:0x11:0x1e5bb2fa:0x0d6>
ld0: 14980 MB, 7608 cyl, 64 head, 63 sec, 512 bytes/sect x 30679040 sectors
ld1: 8-bit width, 52.000 MHz
ld0: 27890816 trailing sectors not covered by disklabel
ld0: 4-bit width, High-Speed/SDR25, 50.000 MHz