Launched in 2004, dmesgd aims to provide a user-submitted repository of searchable *BSD dmesgs. The dmesg(8) command displays the system message buffer's content, and during boot a copy is saved to /var/run/dmesg.boot. This buffer contains the operating system release, name and version, a list of devices identified, plus a whole host of other useful information. We hope others find this resource useful and further contribute to its growth. Contact us at [ admin at lists dot nycbug dot org ]. Note that this site is not a substitute for sending the dmesg directly to the respective project.
Date: 2019-04-11 00:33:28
From: yamori813
Description: Pcduino_Lite(not stable some time panic)
---<<BOOT>>--- ARM Debug Architecture not supported KDB: debugger backends: ddb KDB: current backend: ddb Copyright (c) 1992-2019 The FreeBSD Project. Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 The Regents of the University of California. All rights reserved. FreeBSD is a registered trademark of The FreeBSD Foundation. FreeBSD 13.0-CURRENT #7 a34b1232771(zrouter)-dirty: Thu Apr 11 09:26:33 JST 2019 hiroki@zrouter:/usr/home/hiroki/zobj/usr/home/hiroki/ZRouter/tmp/usr/home/hi roki/freebsd/arm.armv7/sys/Pcduino_Lite arm FreeBSD clang version 8.0.0 (tags/RELEASE_800/final 356365) (based on LLVM 8.0.0 ) CPU: ARM Cortex-A8 r3p2 (ECO: 0x00000000) CPU Features: Thumb2, Security, VMSAv7 Optional instructions: UMULL, SMULL, SIMD(ext) LoUU:2 LoC:3 LoUIS:1 Cache level 1: 32KB/64B 4-way data cache WT WB Read-Alloc 32KB/64B 4-way instruction cache Read-Alloc Cache level 2: 256KB/64B 8-way unified cache WT WB Read-Alloc Write-Alloc real memory = 536870912 (512 MB) avail memory = 520138752 (496 MB) arc4random: no preloaded entropy cache random: entropy device external interface ofwbus0: <Open Firmware Device Tree> aw_ccu0: <Allwinner Clock Control Unit> on ofwbus0 clk_fixed0: <Fixed clock> on aw_ccu0 clk_fixed1: <Fixed clock> on aw_ccu0 simplebus0: <Flattened device tree simple bus> on ofwbus0 ccu_a10ng0: <Allwinner A10/A20 Clock Control Unit NG> mem 0x1c20000-0x1c203ff on simplebus0 regfix0: <Fixed Regulator> on ofwbus0 regfix1: <Fixed Regulator> on ofwbus0 regfix2: <Fixed Regulator> on ofwbus0 regfix3: <Fixed Regulator> on ofwbus0 regfix4: <Fixed Regulator> on ofwbus0 regfix5: <Fixed Regulator> on ofwbus0 aw_sid0: <Allwinner Secure ID Controller> mem 0x1c23800-0x1c2380f on simplebus0 aintc0: <A10 AINTC Interrupt Controller> mem 0x1c20400-0x1c207ff on simplebus0 gpio0: <Allwinner GPIO/Pinmux controller> mem 0x1c20800-0x1c20bff irq 21 on simp lebus0 gpiobus0: <OFW GPIO bus> on gpio0 a10_timer0: <Allwinner timer> mem 0x1c20c00-0x1c20c8f irq 22 on simplebus0 Event timer "a10_timer Eventtimer" frequency 24000000 Hz quality 1000 Timecounter "a10_timer timer0" frequency 24000000 Hz quality 1000 rtc0: <Allwinner RTC> mem 0x1c20d00-0x1c20d1f irq 23 on simplebus0 rtc0: registered as a time-of-day clock, resolution 1.000000s awusbphy0: <Allwinner USB PHY> mem 0x1c13400-0x1c1340f,0x1c14800-0x1c14803,0x1c1 c800-0x1c1c803 on simplebus0 cpulist0: <Open Firmware CPU Group> on ofwbus0 cpu0: <Open Firmware CPU> on cpulist0 a10dmac0: <Allwinner DMA controller> mem 0x1c02000-0x1c02fff irq 0 on simplebus0 aw_mmc0: <Allwinner Integrated MMC/SD controller> mem 0x1c0f000-0x1c0ffff irq 7 on simplebus0 mmc0: <MMC/SD bus> on aw_mmc0 ohci0: <Generic OHCI Controller> mem 0x1c14400-0x1c144ff irq 13 on simplebus0 usbus0 on ohci0 ohci1: <Generic OHCI Controller> mem 0x1c1c400-0x1c1c4ff irq 19 on simplebus0 usbus1 on ohci1 gpioc0: <GPIO controller> on gpio0 aw_wdog0: <Allwinner A10 Watchdog> mem 0x1c20c90-0x1c20c9f on simplebus0 aw_ts0: <Allwinner Touch Screen controller> mem 0x1c25000-0x1c250ff irq 30 on si mplebus0 uart0: <16750 or compatible> mem 0x1c28000-0x1c283ff irq 31 on simplebus0 uart0: console (115384,n,8,1) Timecounters tick every 10.000 msec usbus0: 12Mbps Full Speed USB v1.0 usbus1: 12Mbps Full Speed USB v1.0 ugen1.1: <Generic OHCI root HUB> at usbus1 uhub0: <Generic OHCI root HUB, class 9/0, rev 1.00/1.00, addr 1> on usbus1 ugen0.1: <Generic OHCI root HUB> at usbus0 uhub1: <Generic OHCI root HUB, class 9/0, rev 1.00/1.00, addr 1> on usbus0 mmcsd0: 8GB <SDHC SA08G 0.4 SN 9C800172 MFG 05/2010 by 2 TM> at mmc0 50.0MHz/4bi t/4096-block Trying to mount root from cd9660:/dev/mmcsd0s2 []... mmc0: Failed to set VCCQ for card at relative address 4660 WARNING: geom_mbr (geom mmcsd0) is deprecated, use gpart instead. uhub0: 1 port with 1 removable, self powered uhub1: 1 port with 1 removable, self powered random: read_random_uio unblock wait random: read_random_uio unblock wait random: unblocking device. lo0: link state changed to UP /tmp: optimization changed from SPACE to TIME