Launched in 2004, dmesgd aims to provide a user-submitted repository of searchable *BSD dmesgs. The dmesg(8) command displays the system message buffer's content, and during boot a copy is saved to /var/run/dmesg.boot. This buffer contains the operating system release, name and version, a list of devices identified, plus a whole host of other useful information. We hope others find this resource useful and further contribute to its growth. Contact us at [ admin at lists dot nycbug dot org ]. Note that this site is not a substitute for sending the dmesg directly to the respective project.
Date: 2022-11-20 06:54:18
From: yamori813
Description: ORION hangup
## Transferring control to NetBSD stage-2 loader (at address 00400040) ... [ 1.0000000] NetBSD/evbarm (mv2120) booting ... [ 1.0000000] [ Kernel symbol table missing! ] [ 1.0000000] Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, [ 1.0000000] 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, [ 1.0000000] 2018, 2019, 2020, 2021, 2022 [ 1.0000000] The NetBSD Foundation, Inc. All rights reserved. [ 1.0000000] Copyright (c) 1982, 1986, 1989, 1991, 1993 [ 1.0000000] The Regents of the University of California. All rights reserved. [ 1.0000000] NetBSD 9.3 (MV2120) #0: Sun Nov 20 15:38:28 JST 2022 [ 1.0000000] hiroki@netbsd:/usr/home/hiroki/NetBSD93/usr/src/sys/arch/evbarm/compile/obj/MV2120 [ 1.0000000] total memory = 32768 KB [ 1.0000000] avail memory = 24708 KB [ 1.0000000] running cgd selftest aes-xts-256 aes-xts-512 done [ 1.0000000] mainbus0 (root) [ 1.0000000] cpu0 at mainbus0 core 0: ARM926EJ-S rev 0 (ARM9EJ-S V5TEJ core) [ 1.0000000] cpu0: DC enabled IC enabled WB enabled LABT [ 1.0000000] cpu0: 32KB/32B 1-way L1 VIVT Instruction cache [ 1.0000000] cpu0: 32KB/32B 1-way write-back-locking-C L1 VIVT Data cache [ 1.0000000] mvsoc0 at mainbus0: Marvell MV88F5181 Rev. B1 Orion1 [ 1.0000000] mvsoc0: CPU Clock 500.000 MHz SysClock 166.666 MHz TClock 166.666 MHz [ 1.0000000] mvsoctmr0 at mvsoc0 unit 0 offset 0x20300-0x203ff irq 33: Marvell SoC Timer [ 1.0000000] mvsocgpp0 at mvsoc0 unit 0 offset 0x10100-0x101ff irq 6: Marvell SoC General Purpose I/O Port Interface [ 1.0000000] mvsocgpp0: 32 gpio pins [ 1.0000000] mvsocgpp0: interrupts 64..71, intr 6 [ 1.0000000] mvsocgpp0: interrupts 72..79, intr 7 [ 1.0000000] mvsocgpp0: interrupts 80..87, intr 8 [ 1.0000000] mvsocgpp0: interrupts 88..95, intr 9 [ 1.0000000] mvsocgpp0: Data Out: 0x00e00005 [ 1.0000000] mvsocgpp0: Data Out Enable Control: 0xff1f075f [ 1.0000000] mvsocgpp0: Data Blink Enable: 0x00000000 [ 1.0000000] mvsocgpp0: Data In Polarity: 0x00000530 [ 1.0000000] mvsocgpp0: Data In: 0x00e0046d [ 1.0000000] mvsocgpp0: Interrupt Cause: 0x00000000 [ 1.0000000] mvsocgpp0: Interrupt Mask: 0x00000000 [ 1.0000000] mvsocgpp0: Interrupt Level Mask: 0x00000000 [ 1.0000000] gpio0 at mvsocgpp0: 32 pins [ 1.0000000] com0 at mvsoc0 unit 0 offset 0x12000-0x1201f irq 3: ns16550a, working fifo [ 1.0000000] com0: console [ 1.0000000] com1 at mvsoc0 unit 1 offset 0x12100-0x1211f irq 4: ns16550a, working fifo [ 1.0000000] ehci0 at mvsoc0 unit 0 offset 0x50000-0x50fff irq 17: Marvell USB 2.0 Interface