Launched in 2004, dmesgd aims to provide a user-submitted repository of searchable *BSD dmesgs. The dmesg(8) command displays the system message buffer's content, and during boot a copy is saved to /var/run/dmesg.boot. This buffer contains the operating system release, name and version, a list of devices identified, plus a whole host of other useful information. We hope others find this resource useful and further contribute to its growth. Contact us at [ admin at lists dot nycbug dot org ].
Date: 2023-05-27 15:58:47
From: jklos
Description: Orange Pi 5
[ 1.0000000] NetBSD/evbarm (fdt) booting ...
[ 1.0000000] Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
[ 1.0000000] 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013,
[ 1.0000000] 2014, 2015, 2016, 2017, 2018, 2019, 2020, 2021, 2022, 2023
[ 1.0000000] The NetBSD Foundation, Inc. All rights reserved.
[ 1.0000000 1.0000000] NetBSD 10.99.2 (GENERIC64) #20: Wed Apr 5 16:03:08 CEST 2023
[ 1.0000000] cypheon@beltix:/home/cypheon/obj-aarch64/sys/arch/evbarm/compile/GENERIC64
[ 1.0000000] total memory = 16099 MB
[ 1.0000000] avail memory = 15520 MB
[ 1.0000000] armfdt0 (root)
[ 1.0000000] simplebus0 at armfdt0: Radxa ROCK 5 Model B
[ 1.0000000] cpus0 at simplebus0
[ 1.0000000] simplebus1 at simplebus0
[ 1.0000000] mmiosram0 at simplebus0: MMIO SRAM
[ 1.0000000] mmiosram1 at simplebus0: MMIO SRAM
[ 1.0000000] mmiosram2 at simplebus0: MMIO SRAM
[ 1.0000000] psci0 at simplebus0: PSCI 1.1
[ 1
[ 1.0000000] cpu0 at cpus0: Arm Cortex-A55 r2p0 (v8.2-A+), id 0x0
[ 1.0000000] cpu0: package 0, core 0, smt 0
[ 1.0000000] cpu1 at cpus0: Arm Cortex-A55 r2p0 (v8.2-A+), id 0x100
[ 1.0000000] cpu1: package 0, core 1, smt 0
[ 1.0000000] cpu2 at cpus0: Arm Cortex-A55 r2p0 (v8.2-A+), id 0x200
[ 1.0000000] cpu2: package 0, core 2, smt 0
[ 1.0000000] cpu3 at cpus0: Arm Cortex-A55 r2p0 (v8.2-A+), id 0x300
[ 1.0000000[ 1.0000000] cpu4 at cpus0: Arm Cortex-A76 r4p0 (v8.2-A+), id 0x400
[ 1.0000000] cpu4: package 0, core 4, smt 0
[ 1.0000000] cpu5 at cpus0: Arm Cortex-A76 r4p0 (v8.2-A+), id 0x500
[ 1.0000000] cpu5: package 0, core 5, smt 0
[ 1.0000000] cpu6 [ 1.0000000] cpu7 at cpus0: Arm Cortex-A76 r4p0 (v8.2-A+), id 0x700
[ 1.0000000] cpu7: package 0, core 7, smt 0
[ 1.0000000] scmi_shmem0 at mmiosram0: ARM SCMI Shared Memory Transport (0x0 + 0x100)
[ 1.0000000] gicvthree0 at simplebus0: GICv3
[ 1.0000000] gicvthree0: MBI frame @ 0xfe610000, SPIs 424-479
[ 1.0000000] scmi0 at simplebus1: ARM SCMI
[ 1.0000000] scmi_clk0 at scmi0: ARM SCMI Clock Controller
[ 1.0000000] scmi_clk0: set clk rate (scmi_clk_cpub01, 2) <- 1200000000
[ 1.0000000] scmi_clk0: set rate status: 0
[ 1.0000000] scmi_clk0: [ 1.0000000] protocol id 0x125bfc8 at scmi0 not configured
[ 1.0000000] syscon0 at simplebus0: System Controller Registers
[ 1.0000000] syscon1 at simplebus0: System Controller Registers
[ 1.0000000] syscon2 at simplebus0: System Controller Registers
[ 1.0000000] syscon3 at simplebus0: System Controller Registers
[ 1.0000000] syscon4 at simplebus0: System Controller Registers
[ 1.0000000] syscon5 at simplebus0: System Controller Registers
[ 1.0000000] syscon6 at simpleb 1.0000000] syscon7 at simplebus0: System Controller Registers
[ 1.0000000] syscon8 at simpleb: System Controller Registers
[ 1.0000000] syscon9 at simplebus0: System Controller Registers
[ 1.0000000] syscon10 at simple: System Controller Registers
[ 1.0000000] syscon11 at simplebus0: System Controller Registers
[ 1.0000000] syscon12 at simplebus0: System Controller Registers
[ 1.0000000] syscon13 at simplebus0: System Controller Registers
[ 1.0000000] sysconlebus0: System Controller Registers
[ 1.0000000] syscon15 at simple simplebus0: System Controller Registers
[ 1.0000000] syscon18 at simple: System Controller Registers
[ 1.0000000] syscon19 at simplebus0: System Controller Registers
[ 1.0000000] syscon20 at simplebus0: System Controller Registers
[ 1.0000000] syscon21 at simple: System Controller Registers
[ 1.0000000] syscon22 at simplebus0: System Controller Registers
[ 1.0000000] syscon23 at simple: System Controller Registers
[ 1.0000000] syscon24 at simplebus0: System Controller Registers
[ 1.0000000] syscon25 at simple: System Controller Registers
[ 1.0000000] syscon26 at simplebus0: System Controller Registers
[ 1.0000000] syscon27 at simple: System Controller Registers
[ 1.0000000] syscon29 at simplebus0: System Controller Registers
[ 1.0000000] syscon30 at simple0: System Controller Registers
[ 1.0000000] syscon31 at simplebus0: System Controller Registers
[ 1.0000000] syscon32 at simple: System Controller Registers
[ 1.0000000] syscon33 at simplebus0: System Controller Registers
[ 1.0000000] syscon34 at simple: System Controller Registers
[ 1.0000000] syscon35 at simplebus0: System Controller Registers
[ 1.0000000] syscon36 at simple: System Controller Registers
[ 1.0000000] syscon37 at simplebus0: System Controller Registers
[ 1.0000000] syscon38 at simplebus0: System Controller Registers
[ 1.0000000] syscon39 at simplebus0: System Controller Registers
[ 1.0000000] syscon40 at simple[ 1.0000000] syscon41 at simplebus0: System Controller Registers
[ 1.0000000] syscon42 at simple: System Controller Registers
[ 1.0000000] syscon43 at simplebus0: System Controller Registers
[ 1.0000000] syscon44 at simplebus0: System Controller Registers
[ 1.0000000] syscon45 at simplebus0: System Controller Registers
[ 1.0000000] syscon46 at simplebus0: System Controller Registers
[ 1.0000000] syscon47 at simplebus0: System Controller Registers
[ 1.0000000] syscon48 at simplebus0: System Controller Registers
[ 1.0000000] syscon49 at simplebus0: System Controller Registers
[ 1 syscon50 at simplebus0: System Controller Registers
[ 1.0000000] syscon51 at simplebus0: System Controller Registers
[ 1.0000000] syscon52 at simplebus0: System Controller Registers
[ 1.0000000] syscon53 at simplebus0: System Controller Registers2000000 Hz fixed clock (spll)
[ 1.0000000] fclock1 at simplebus0: 24000000 Hz fixed clock (xin24m)
[ 1.0000000] fclock2 at simplebus0: 32768 Hz fixed clock (xin32k)
[ 1.0000000] syscon55 at simplebus0: System Controller Registers
[ 1.0000000] s: System Controller Registers
[ 1.0000000] fclock3 at simplebus0: 12000000 Hz fixed clock (xin12m)
[ 1.0000000] rkcru0 at simplebus0: RK3588 CRU
[ 1.0000000] gtmr0 at simplebus0: Generic Timer
[ 1.0000000] gtmr0: interrupting on GICv3 irq 27
[ 1.0000000 at gtmr0: Generic Timer (24000 kHz, virtual)
[ 1.0000040] rkiomux0 at simplebus0: RK3588 IOMUX control
[ 1.0000040] rkgpio0 at rkiomux0: GPIO v2 (gpio@fd8a0000)
[ 1.0000040] gpio0 at rkgpio0: 32 pins
[ 1.0000040] rkgpio1 at rkiomux0: GPIO v2 (gpio@fec20000)
[ 1.0000040] gpio1 at rkgpio1: 32 pins
[ 1.0000040] rkgpio2 at rkiomux0: GPIO v2 (gpio@fec30000)
[ 1.0000040] gpio2 at rkgpio2: 32 pins
[ 1.0000040] rkgpio3 at rkiomux0: GPIO v2 (gpio@fec40000)
[ 1.0000040] gpio3 at rkgpio3: 32 p: GPIO v2 (gpio@fec50000)
[ 1.0000040] gpio4 at rkgpio4: 32 pins
[ 1.0000040] fregulator0 at simplebus0: vcc5v0_sys
[ 1.0000040] com0 at simplebus0: DesignWare APB UART, 64-byte FIFO
[ 1.0000040] com0: console
[ 1.0000040] com0: interrupting on GICv3 irq 365
[ 1.0000040] fregulator1 at simplebus0: vcc5v0_host
[ 1.0000040] rkusb0 at syscon1: USB2 PHY
[ 1.0000040] : trying to ASSERT reset #0
[ 1.0000040] : trying to de-assert reset #0
[ 1.0000040] : trying to ASSERT reset #1
[ 1.0000040] : trying to de-assert reset #1
[ 1.0000040] soft_con_sel set to `1`, err: 0
[ 1.0000040] rkusbphy0 at rkusb0: USB2 host
[ 1.0000040] : trying to de-assert reset #0
[ 1.0000040] : trying to ASSERT reset #1
[ 1.0000040] : trying to de-assert reset #1
[ 1.0000040] soft_con_sel set to `1`, err: 0
[ 1.0000040] rkusbphy1 at rkusb1: USB2 host port
[ 1.0000040] ohci0 at simplebus0got registers: fc840000, 40000
[ 1.0000040] enabled clock #0
[ 1.0000040] enabled clock #1
[ 1.0000040] rk3588 usb clk_enable: maybe implemented??: 32768 -> 0
[ 1.0000040] enabled clock #2
[ 1.0000040] reset count: 0
2-phy
[ 1.0000040] rk3588 usb host_enable: not implemented, faking success
[ 1.0000040] : OHCI
[ 1.0000040] will disable interrupts: 0xffff0003fafd7b80, 18446744073466544128
[ 1.0000040] decoded intrstr
[ 1.0000040] ohci0: interrupting on GIion 1.0
[ 1.0000040] usb0 at ohci0: USB revision 1.0
[ 1.0000040] /power-management@fd8d8000/power-controller at sy[ 1.0000040] ohci1 at simplebus0got registers: fc8c0000, 40000
[ 1.0000040] enabled clock #0
[ 1.0000040] enabled clock #1
[ 1.0000040] rk3588 usb clk_enable: maybe implemented??: 49152 -> 0
[ 1.0000040] reset count: 0#2
[[ 1.0000040] OHCI: got usb2-phy
[ 1.0000040] rk3588 usb host_enable: not implemented, faking success
[ 1.0000040] : OHCI
[ 1.0000040] will disable interrupts: 0xffff0003fafac500, 18446744073467068416
[ 1.0000040] decoded intrstr
[ 1.0000040] ohci1: interrupting on GICv3 irq 251
[ 1.0000040] ohci1: OHCI version 1.0
[ 1.0000040] usb1 at ohci1: USB revision 1.0
[ 1.0000040] /dma-controller@fea10000 at simplebus0 not config[ 1.0000040] /dma-controller@fea30000 at simplebus0 not configured
[ 1.0000040] /dma-controller@fed10000 at simplebus0 not configured
[ 1.0000040] /firmware/optee at simplebus1 not configured
[ 1.0000040] ehci0 at simplebus0rk3588 usb clk_enable: maybe implemented??: 32768 -> 0
[ 1.0000040] rk3588 usb host_enable: not implemented, faking s[ 1.0000040] ehci0: interrupting on GICv3 irq 247
[ 1.0000040] ehci0: 1 companion controller, 1 port
[ 1.0000040] ehci0: Using DMA subregion for control data structures
[ 1.0000040] usb2 at ehci0: USB revision 2.0
[ 1.0000040] ehci1 at simplebus0rk3588 usb clk_enable: maybe implemented??: 49152 -> 0
[ 1.0000040] rk3588 usb host_enable: not implemented, faking sess
[ 1.0000040] : EHCI
[ 1.0000040] ehci1: interrupting on GICv3 irq 250
[ 1.00000040] ehci1: Using DMA subregion for control data structures
[ 1.0000040] usb3 at ehci1: USB revision 2.0
[ 1.0000040] dwcmmc0 at simplebus0: DesignWare SD/MMC
[ 1.0000040] dwcmmc0: interrup[ 1.0000040] dwcmshc0 at simplebus0core clock HARD set to 200 MHz
[ 1.0000040] : DWCMSHC SDHC Controller
[ 1.0000040] got clock bus -> 198000000 Hz
[ 1.0000040] got clock core -> 198000000 Hz
[ 1.0000040] got clock axi -> 300000000 Hz
[ 1.0000040] got clock block -> 198000000 Hz
[ 1.0000040] got clock timer -> 24000000 Hz
[ 1.000004[ 1.0000040] got core reset: 0xffff0003fa843560
[ 1.0000040] got core reset: 0xffff0003fa843520
[ 1.0000040] got core reset: 0xffff0003fa8435a0
[ 1.0000040[ 1.0000040] dwcmshc0: interrupting on GICv3 irq 237
[ 1.0000040] dwcmshc0: SDHC 4.2, rev 0, 32-bit ADMA2, 198000 kHz, HS SDR50 DDR50 SDR104 HS200 3.0V, re-tuning mode 1, 1024 byte blocks
[ 1.0000040] sdmmc0 at dwcmshc0 slot 0
[ 1.0000040] /hdmilebus0 not configured
[ 1.0000040] /pmu-a55 at simplebus0 not configured
[ 1.0000040] /pmu-a76 at simplebus0 not configured
[ 1.9589471] sdmmc1 at dwcmmc0
[ 1.9589471] scmi_clk0: set clk rate (scmi_cclk_sd, 9) <- 800000
[ 1.9589471] scmi_clk0: set rate status: 0
[ 1.9589471] scmi_clk0: get clk rate (scmi_cclk_sd, 9)
[ 1.9589471] scmi_clk0: get rate status: 0, rate: 800000
[ 1.9589471] dwcmshc0: : vendor_hw_reset begin
[ .9589471] dwcmshc0: : emmcctrl HW RESET asserted
[ 1.9589471] dwcmshc0: : emmcctrl HW RESET deasserted
[ 1.9589471] dwcmshc0: : emmc dll ctrl before=0
[ 1.9589471] dwcmshc0: : emmc dll rxclk before=0
[ 1.9589471] dwcmshc0: : emmc dll txclk befommc dll ctrl after=1000000
[ 1.9589471] dwcmshc0: : emmc dll rxclk after=0
[ 1.9589471] dwcmshc0: : emmc dll txclk after=0
[ 1.9589471] dwcmshc0: : emmc dll strbin after=0
[ 1.9589471] dwcmshc0: : emmc dll cmdout after=0
[ 1.9789493] dwcmshc0: vendor_bus_clock clock has been set to 400000 Hz
[ 1.9789493] uhub0 at usb0: NetBSD (0x0000) OHCI root hub (0x0000), class 9/0, rev 1.00/1.00, addr 1
[ 1.9789493] uhub3 at usb2: NetBSD (0x0000) EHCI root hub (0x0000), class 9/0, rev 2.00/1.00, addr 1
[ 1.9789493] WARNING: system needs 1.9789493] uhub1 at usb1: NetBSD (0x0000) OHCI root hub (0x0000), class 9/0, rev 1.00/1.00, addr 1
[ 1.9789493] uhub2 at usb3: NetBSD (0x0000) EHCI root hub (0x0000), class 9/0, rev 2.00/1.00, addr 1
[ 2.0689539] scmi_clk0: set clk rate (scmi_cclk_sd, 9) <- 50000000
[ 2.0689539] scmi_clk0: set rate status: 0
[ 2.0689539] scmi_clk0: get clk rate (scmi_cclk_sd, 9)
[ 2.0689539] scmi_clk0: get rate status: 0, rate: 49500000
[ 2.0889543] scmi_clk0: set clk rate (scmi_cclk_sd, 9) <- 100000000
[ 2.0889543] scmi_clk0: set rate status: 0
[ 2.0889543] scmi_clk0: get clk rate (scmi_cclk_sd, 9)
[ 2.0889543] scmi_clk0: get rate status: 0, rate: 99000000
[ 2.0989541] sdmmc1: SD card status: 4-bit, C10, U1, V10
[ 2.0989541] ld1 at sdmmc1: <0x27:0x5048:SD32G:0x60:0x3e281c60:0x169>
[ 2.1089548] ld1: 29554 MB, 7505 cyl, 128 head, 63 sec, 512 bytes/sect x 60526592 sectors
[ 2.1189543] dwcmshc0: vendor_bus_clock clock has been set to 375000 Hz
[ 2.1289558] sdmmc0: couldn't enable card: 60
[ 2.1289558] dwcmshc0: vendor_bus_clock clock has been set to 375000 Hz
[ 2.1389556] dk0 at ld1: "EFI", 163840 blocks at 32768, type: DR25, 50.000 MHz
[ 2.4889734] swwdog0: software watchdog initialized
[ 2.4889734] WARNING: 1 error while detecting hardware; check [ 2.4889734] root on dk1
[ 2.4989741] root file system type: ffs
[ 2.5089742] kern.module.path=/stand/evbarm/10.99.2/modules