Launched in 2004, dmesgd aims to provide a user-submitted repository of searchable *BSD dmesgs. The dmesg(8) command displays the system message buffer's content, and during boot a copy is saved to /var/run/dmesg.boot. This buffer contains the operating system release, name and version, a list of devices identified, plus a whole host of other useful information. We hope others find this resource useful and further contribute to its growth. Contact us at [ admin at lists dot nycbug dot org ]. Note that this site is not a substitute for sending the dmesg directly to the respective project.

Date: 2026-01-14 15:47:02
From: zauq
Description: OpenBSD 7.8 on Orange Pi Zero 2
OpenBSD 7.8 (GENERIC.MP) #1: Sat Nov 29 11:06:26 MST 2025
    [_EMAIL_XXXXXXXXXXXXXXXXXXXXXXXXX]:/usr/src/sys/arch/arm64/compile/GENERIC.MP
real mem  = 1071882240 (1022MB)
avail mem = 998113280 (951MB)
random: good seed from bootblocks
mainbus0 at root: OrangePi Zero2
psci0 at mainbus0: PSCI 1.1, SMCCC 1.4
efi0 at mainbus0: UEFI 2.10
efi0: Das U-Boot rev 0x20240100
smbios0 at efi0: SMBIOS 3.0
smbios0: vendor U-Boot version "2024.01" date 01/01/2024
smbios0: Unknown Unknown Product
cpu0 at mainbus0 mpidr 0: ARM Cortex-A53 r0p4
cpu0: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 D-cache
cpu0: 256KB 64b/line 16-way L2 cache
cpu0: CRC32,SHA2,SHA1,AES+PMULL,ASID16
cpu1 at mainbus0 mpidr 1: ARM Cortex-A53 r0p4
cpu1: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 D-cache
cpu1: 256KB 64b/line 16-way L2 cache
cpu2 at mainbus0 mpidr 2: ARM Cortex-A53 r0p4
cpu2: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 D-cache
cpu2: 256KB 64b/line 16-way L2 cache
cpu3 at mainbus0 mpidr 3: ARM Cortex-A53 r0p4
cpu3: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 D-cache
cpu3: 256KB 64b/line 16-way L2 cache
"secmon" at mainbus0 not configured
apm0 at mainbus0
"osc24M-clk" at mainbus0 not configured
"pmu" at mainbus0 not configured
agtimer0 at mainbus0: 24000 kHz
simplebus0 at mainbus0: "soc"
sxisyscon0 at simplebus0
sxiccmu0 at simplebus0
sxisid0 at simplebus0
sxipio0 at simplebus0: 85 pins
ampintc0 at simplebus0 nirq 192, ncpu 4 ipi 0: "interrupt-controller"
sxirtc0 at simplebus0
sxiccmu1 at simplebus0
sxipio1 at simplebus0: 2 pins
sxirsb0 at simplebus0
axppmic0 at sxirsb0 addr 0x745: AXP305
"crypto" at simplebus0 not configured
"dma-controller" at simplebus0 not configured
sxidog0 at simplebus0
"iommu" at simplebus0 not configured
sximmc0 at simplebus0
sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma
com0 at simplebus0: dw16550
com0: console
"spi" at simplebus0 not configured
dwxe0 at simplebus0: address [_MAC_XXXXXXXXXX]
rgephy0 at dwxe0 phy 1: RTL8169S/8110S/8211, rev. 6
"thermal-sensor" at simplebus0 not configured
"codec" at simplebus0 not configured
"usb" at simplebus0 not configured
"phy" at simplebus0 not configured
ehci0 at simplebus0
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00 addr 1
ohci0 at simplebus0: version 1.0
"interrupt-controller" at simplebus0 not configured
gpio0 at sxipio0: 32 pins
gpio1 at sxipio0: 32 pins
gpio2 at sxipio0: 32 pins
gpio3 at sxipio0: 32 pins
gpio4 at sxipio0: 32 pins
gpio5 at sxipio0: 32 pins
gpio6 at sxipio0: 32 pins
gpio7 at sxipio0: 32 pins
gpio8 at sxipio0: 32 pins
gpio9 at sxipio1: 32 pins
usb1 at ohci0: USB revision 1.0
uhub1 at usb1 configuration 1 interface 0 "Generic OHCI root hub" rev 1.00/1.00 addr 1
gpioleds0 at mainbus0: "power"
"vcc5v" at mainbus0 not configured
"regulator-usb1-vbus" at mainbus0 not configured
"opp-table-cpu" at mainbus0 not configured
scsibus0 at sdmmc0: 2 targets, initiator 0
sd0 at scsibus0 targ 1 lun 0: <Sandisk, SR64G, 0080> removable
sd0: 60906MB, 512 bytes/sector, 124735488 sectors
vscsi0 at root
scsibus1 at vscsi0: 256 targets
softraid0 at root
scsibus2 at softraid0: 256 targets
root on sd0a (9582be3c3b094f1e.a) swap on sd0b dump on sd0b
WARNING: / was not properly unmounted
WARNING: bad clock chip time
WARNING: CHECK AND RESET THE DATE!