Launched in 2004, dmesgd aims to provide a user-submitted repository of searchable *BSD dmesgs. The dmesg(8) command displays the system message buffer's content, and during boot a copy is saved to /var/run/dmesg.boot. This buffer contains the operating system release, name and version, a list of devices identified, plus a whole host of other useful information. We hope others find this resource useful and further contribute to its growth. Contact us at [ admin at lists dot nycbug dot org ].
Date: 2017-09-22 19:10:49
From: skibo
Description: FreeBSD 11.1-RELEASE on a Zybo
Copyright (c) 1992-2017 The FreeBSD Project. Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 The Regents of the University of California. All rights reserved. FreeBSD is a registered trademark of The FreeBSD Foundation. FreeBSD 11.1-RELEASE #0 r323367: Sat Sep 9 12:06:09 PDT 2017 skibo@ashbury:/usr/home/skibo/crochet-freebsd/work/obj/arm.armv6/usr/src/sys/ZEDBOARD arm FreeBSD clang version 4.0.0 (tags/RELEASE_400/final 297347) (based on LLVM 4.0.0) CPU: ARM Cortex-A9 r3p0 (ECO: 0x00000000) CPU Features: Multiprocessing, Thumb2, Security, VMSAv7, Coherent Walk Optional instructions: UMULL, SMULL, SIMD(ext) LoUU:2 LoC:2 LoUIS:2 Cache level 1: 32KB/32B 4-way data cache WB Read-Alloc Write-Alloc 32KB/32B 4-way instruction cache Read-Alloc real memory = 536866816 (511 MB) avail memory = 515215360 (491 MB) FreeBSD/SMP: Multiprocessor System Detected: 2 CPUs random: entropy device external interface ofwbus0: <Open Firmware Device Tree> simplebus0: <Flattened device tree simple bus> on ofwbus0 simplebus1: <Flattened device tree simple bus> on ofwbus0 l2cache0: <PL310 L2 cache controller> mem 0xf02000-0xf02fff irq 0 on simplebus0 l2cache0: cannot allocate IRQ, not using interrupt l2cache0: Part number: 0x3, release: 0x8 l2cache0: L2 Cache enabled: 512KB/32B 8 ways gic0: <ARM Generic Interrupt Controller> mem 0xf01000-0xf01fff,0xf00100-0xf001ff on simplebus0 gic0: pn 0x390, arch 0x1, rev 0x2, implementer 0x43b irqs 96 mp_tmr0: <ARM MPCore Timers> mem 0xf00200-0xf002ff,0xf00600-0xf0061f irq 2,3 on simplebus0 Timecounter "MPCore" frequency 325000000 Hz quality 800 Event timer "MPCore" frequency 325000000 Hz quality 1000 zy7_slcr0: <Zynq-7000 slcr block> mem 0-0xfff on simplebus0 zy7_devcfg0: <Zynq devcfg block> mem 0x7000-0x7fff irq 1 on simplebus0 uart0: <Cadence UART> mem 0x1000-0x1fff irq 7 on simplebus1 uart0: console (-1,n,8,1) ehci0: <Zynq-7000 EHCI USB 2.0 controller> mem 0x2000-0x2fff irq 8 on simplebus1 usbus0: EHCI version 1.0 usbus0: stop timeout usbus0 on ehci0 gpio0: <Zynq-7000 GPIO driver> mem 0xa000-0xafff irq 10 on simplebus1 gpiobus0: <GPIO bus> on gpio0 gpioc0: <GPIO controller> on gpio0 cgem0: <Cadence CGEM Gigabit Ethernet Interface> mem 0xb000-0xbfff irq 11 on simplebus1 miibus0: <MII bus> on cgem0 rgephy0: <RTL8169S/8110S/8211 1000BASE-T media interface> PHY 0 on miibus0 rgephy0: none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT-FDX, 1000baseT-FDX-master, auto rgephy1: <RTL8169S/8110S/8211 1000BASE-T media interface> PHY 1 on miibus0 rgephy1: none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT-FDX, 1000baseT-FDX-master, auto cgem0: Ethernet address: [_MAC_XXXXXXXXXX] sdhci_fdt0: <Zynq-7000 generic fdt SDHCI controller> mem 0x100000-0x100fff irq 14 on simplebus1 sdhci_fdt0: 1 slot(s) allocated mmc0: <MMC/SD bus> on sdhci_fdt0 cryptosoft0: <software crypto> Timecounters tick every 1.000 msec usbus0: 480Mbps High Speed USB v2.0 ugen0.1: <Xilinx EHCI root HUB> at usbus0 uhub0: <Xilinx EHCI root HUB, class 9/0, rev 2.00/1.00, addr 1> on usbus0 mmcsd0: 8GB <SDHC SU08G 8.0 SN 0623235C MFG 03/2013 by 3 SD> at mmc0 50.0MHz/4bit/65535-block Release APs Trying to mount root from ufs:/dev/mmcsd0s2a [rw,noatime]... warning: no time-of-day clock registered, system time will not be set accurately uhub0: 1 port with 1 removable, self powered random: unblocking device. cgem0: link state changed to DOWN cgem0: link state changed to UP