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Date: 2018-10-26 13:19:23
From: jmcneill
Description: NetBSD/evbarm 8.0 on Hardkernel ODROID-C1
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
    2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017,
    2018 The NetBSD Foundation, Inc.  All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
    The Regents of the University of California.  All rights reserved.

NetBSD 8.0 (ODROID-C1) #0: Tue Jul 17 14:59:51 UTC 2018
        [_EMAIL_XXXXXXXXXXXXXXXXX]:/usr/src/sys/arch/evbarm/compile/ODROID-C1
total memory = 1024 MB
avail memory = 1007 MB
sysctl_createv: sysctl_create(machine_arch) returned 17
timecounter: Timecounters tick every 10.000 msec
mainbus0 (root)
cpu0 at mainbus0 core 0: 1536 MHz Cortex-A5 r0p1 (Cortex V7A core)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB/32B 2-way L1 VIPT Instruction cache
cpu0: 32KB/32B 4-way write-back-locking-C L1 PIPT Data cache
cpu0: 512KB/32B 8-way write-back L2 PIPT Unified cache
vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
cpu1 at mainbus0 core 1
cpu2 at mainbus0 core 2
cpu3 at mainbus0 core 3
armperiph0 at mainbus0
armgic0 at armperiph0: Generic Interrupt Controller, 256 sources (245 valid)
armgic0: 32 Priorities, 224 SPIs, 5 PPIs, 16 SGIs
a9tmr0 at armperiph0: A5 Global 64-bit Timer (384 MHz)
a9tmr0: interrupting on irq 27
a9wdt0 at armperiph0: A5 Watchdog Timer, default period is 12 seconds
arml2cc0 at armperiph0: ARM PL310 r3p3 L2 Cache Controller (disabled)
arml2cc0: cache enabled
amlogicio0 at mainbus0
amlogiccom0 at amlogicio0 port 0: console
amlogiccom0: interrupting at irq 122
amlogicgpio0 at amlogicio0: GPIO controller
gpio0 at amlogicgpio0 (GPIOX): 22 pins
gpio1 at amlogicgpio0 (GPIOY): 15 pins
gpio2 at amlogicgpio0 (GPIODV): 30 pins
gpio3 at amlogicgpio0 (GPIOH): 6 pins
gpio4 at amlogicgpio0 (GPIOAO): 14 pins
gpio5 at amlogicgpio0 (BOOT): 19 pins
gpio6 at amlogicgpio0 (CARD): 7 pins
genfb0 at amlogicio0
genfb0: framebuffer at 0xc9e00000, size 1280x720, depth 16, stride 2560
wsdisplay0 at genfb0 kbdmux 1
wsmux1: connecting to wsdisplay0
wsdisplay0: screen 0-3 added (default, vt100 emulation)
amlogicrng0 at amlogicio0
dwctwo0 at amlogicio0 port 0: USB controller
dwctwo1 at amlogicio0 port 1: USB controller
awge0 at amlogicio0: Gigabit Ethernet Controller
awge0: interrupting on irq 40
awge0: Ethernet address: [_MAC_XXXXXXXXXX]
rgephy0 at awge0 phy 0: RTL8169S/8110S/8211 1000BASE-T media interface, rev. 6
rgephy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT-FDX, auto
rgephy1 at awge0 phy 1: RTL8169S/8110S/8211 1000BASE-T media interface, rev. 6
rgephy1: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT-FDX, auto
amlogicsdio0 at amlogicio0: SDIO controller (port B)
amlogicsdio0: interrupting on irq 60
amlogicsdhc0 at amlogicio0: SDHC controller (port C)
amlogicsdhc0: interrupting on irq 110
amlogicrtc0 at amlogicio0: RTC battery not present or discharged
usb0 at dwctwo0: USB revision 2.0
usb1 at dwctwo1: USB revision 2.0
timecounter: Timecounter "clockinterrupt" frequency 100 Hz quality 0
timecounter: Timecounter "a9tmr0" frequency 384000000 Hz quality 500
cpu2: 1536 MHz Cortex-A5 r0p1 (Cortex V7A core)
cpu2: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu2: 32KB/32B 2-way L1 VIPT Instruction cache
cpu2: 32KB/32B 4-way write-back-locking-C L1 PIPT Data cache
cpu2: 512KB/32B 8-way write-back L2 PIPT Unified cache
vfp2 at cpu2: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
cpu1: 1536 MHz Cortex-A5 r0p1 (Cortex V7A core)
cpu1: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu1: 32KB/32B 2-way L1 VIPT Instruction cache
cpu1: 32KB/32B 4-way write-back-locking-C L1 PIPT Data cache
cpu1: 512KB/32B 8-way write-back L2 PIPT Unified cache
vfp1 at cpu1: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
cpu3: 1536 MHz Cortex-A5 r0p1 (Cortex V7A core)
cpu3: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu3: 32KB/32B 2-way L1 VIPT Instruction cache
cpu3: 32KB/32B 4-way write-back-locking-C L1 PIPT Data cache
cpu3: 512KB/32B 8-way write-back L2 PIPT Unified cache
vfp3 at cpu3: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
sdmmc1 at amlogicsdio0
sdmmc0 at amlogicsdhc0
uhub0 at usb0: vendor 0000 (0000) DWC2 root hub (0000), class 9/0, rev 2.00/1.00, addr 1
uhub0: 1 port with 1 removable, self powered
uhub1 at usb1: vendor 0000 (0000) DWC2 root hub (0000), class 9/0, rev 2.00/1.00, addr 1
uhub1: 1 port with 1 removable, self powered
IPsec: Initialized Security Association Processing.
ld0 at sdmmc0: <0x11:0x0100:008G92:0x00:0x9c62cabb:0x000>
ld0: 7456 MB, 3787 cyl, 64 head, 63 sec, 512 bytes/sect x 15269888 sectors
ld0: 8-bit width, HS200, 200.000 MHz
uhub2 at uhub1 port 1: vendor 05e3 (0x5e3) USB2.0 Hub (0x610), class 9/0, rev 2.00/32.98, addr 2
uhub2: multiple transaction translators
uhub2: 4 ports with 4 removable, self powered
uhub1: illegal enable change, port 1
WARNING: 2 errors while detecting hardware; check system log.
boot device: ld0
root on ld0a dumps on ld0b
root file system type: ffs
kern.module.path=/stand/evbarm/8.0/modules
WARNING: no TOD clock present
WARNING: using filesystem time
WARNING: CHECK AND RESET THE DATE!
wsdisplay0: screen 4 added (default, vt100 emulation)