Launched in 2004, dmesgd aims to provide a user-submitted repository of searchable *BSD dmesgs. The dmesg(8) command displays the system message buffer's content, and during boot a copy is saved to /var/run/dmesg.boot. This buffer contains the operating system release, name and version, a list of devices identified, plus a whole host of other useful information. We hope others find this resource useful and further contribute to its growth. Contact us at [ admin at lists dot nycbug dot org ].


Date: 2020-03-10 07:54:22
From: yamori813
Description: Pcduino_Lite fb work fine
---<<BOOT>>---
ARM Debug Architecture not supported
KDB: debugger backends: ddb
KDB: current backend: ddb
Copyright (c) 1992-2020 The FreeBSD Project.
Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
        The Regents of the University of California. All rights reserved.
FreeBSD is a registered trademark of The FreeBSD Foundation.
FreeBSD 12.1-STABLE #229 9c6eed97e20(stable/12)-dirty: Tue Mar 10 16:50:58 JST 2020
    hiroki@zrouter:/usr/home/hiroki/zobj/usr/home/hiroki/ZRouter/tmp/usr/home/hiroki/freebsd/arm.armv7/sys/Pcduino_Lite arm
FreeBSD clang version 9.0.1 (xxx@xxx.xxx:llvm/llvm-project.git c1a0a213378a458fbea1a5c77b315c7dce08fd05) (based on LLVM 9.0.1)
VT: init without driver.
CPU: ARM Cortex-A8 r3p2 (ECO: 0x00000000)
CPU Features: 
  Thumb2, Security, VMSAv7
Optional instructions: 
  UMULL, SMULL, SIMD(ext)
LoUU:2 LoC:3 LoUIS:1 
Cache level 1:
 32KB/64B 4-way data cache WT WB Read-Alloc
 32KB/64B 4-way instruction cache Read-Alloc
Cache level 2:
 256KB/64B 8-way unified cache WT WB Read-Alloc Write-Alloc
real memory  = 536870912 (512 MB)
avail memory = 517963776 (493 MB)
arc4random: no preloaded entropy cache
random: entropy device external interface
ofwbus0: <Open Firmware Device Tree>
ofw_clkbus0: <OFW clocks bus> on ofwbus0
clk_fixed0: <Fixed clock> on ofw_clkbus0
clk_fixed1: <Fixed clock> on ofw_clkbus0
simplebus0: <Flattened device tree simple bus> on ofwbus0
regfix0: <Fixed Regulator> on ofwbus0
regfix1: <Fixed Regulator> on ofwbus0
regfix2: <Fixed Regulator> on ofwbus0
ccu_a10ng0: <Allwinner A10/A20 Clock Control Unit NG> mem 0x1c20000-0x1c203ff on simplebus0
aintc0: <A10 AINTC Interrupt Controller> mem 0x1c20400-0x1c207ff on simplebus0
gpio0: <Allwinner GPIO/Pinmux controller> mem 0x1c20800-0x1c20bff irq 23 on simplebus0
gpiobus0: <OFW GPIO bus> on gpio0
iichb0: <Allwinner Integrated I2C Bus Controller> mem 0x1c2ac00-0x1c2afff irq 43 on simplebus0
iicbus0: <OFW I2C bus> on iichb0
iichb1: <Allwinner Integrated I2C Bus Controller> mem 0x1c2b400-0x1c2b7ff irq 45 on simplebus0
iicbus1: <OFW I2C bus> on iichb1
a10_timer0: <Allwinner timer> mem 0x1c20c00-0x1c20c8f irq 24 on simplebus0
Event timer "a10_timer Eventtimer" frequency 24000000 Hz quality 1000
Timecounter "a10_timer timer0" frequency 24000000 Hz quality 1000
aw_sid0: <Allwinner Secure ID Controller> mem 0x1c23800-0x1c2380f on simplebus0
awusbphy0: <Allwinner USB PHY> mem 0x1c13400-0x1c1340f,0x1c14800-0x1c14803,0x1c1c800-0x1c1c803 on simplebus0
cpulist0: <Open Firmware CPU Group> on ofwbus0
cpu0: <Open Firmware CPU> on cpulist0
a10dmac0: <Allwinner DMA controller> mem 0x1c02000-0x1c02fff irq 1 on simplebus0
emac0: <A10/A20 EMAC ethernet controller> mem 0x1c0b000-0x1c0bfff irq 5 on simplebus0
miibus0: <MII bus> on emac0
rlphy0: <IP101 10/100 PHY> PHY 1 on miibus0
rlphy0:  10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
emac0: Ethernet address: xx:xx:xx:xx:xx:xx
aw_mmc0: <Allwinner Integrated MMC/SD controller> mem 0x1c0f000-0x1c0ffff irq 9 on simplebus0
mmc0: <MMC/SD bus> on aw_mmc0
ehci0: <Generic EHCI Controller> mem 0x1c14000-0x1c140ff irq 14 on simplebus0
usbus0: EHCI version 1.0
usbus0 on ehci0
ohci0: <Generic OHCI Controller> mem 0x1c14400-0x1c144ff irq 15 on simplebus0
usbus1 on ohci0
a10hdmi0: <Allwinner HDMI TX> mem 0x1c16000-0x1c16fff irq 17 on simplebus0
pcm0: <Allwinner HDMI Audio> mem 0x1c16000-0x1c16fff on simplebus0
ehci1: <Generic EHCI Controller> mem 0x1c1c000-0x1c1c0ff irq 20 on simplebus0
usbus2: EHCI version 1.0
usbus2 on ehci1
ohci1: <Generic OHCI Controller> mem 0x1c1c400-0x1c1c4ff irq 21 on simplebus0
usbus3 on ohci1
gpioc0: <GPIO controller> on gpio0
aw_wdog0: <Allwinner A10 Watchdog> mem 0x1c20c90-0x1c20c9f on simplebus0
uart0: <16750 or compatible> mem 0x1c28000-0x1c283ff irq 33 on simplebus0
uart0: console (115384,n,8,1)
iicbus0: <unknown card> at addr 0x68
iic0: <I2C generic I/O> on iicbus0
iic1: <I2C generic I/O> on iicbus1
fb0: <Allwinner Framebuffer> mem 0x1e60000-0x1e6ffff,0x1c0c000-0x1c0cfff,0x1e00000-0x1e1ffff on ofwbus0
gpioled0: <GPIO LEDs> on ofwbus0
Timecounters tick every 10.000 msec
usbus0: 480Mbps High Speed USB v2.0
usbus1: 12Mbps Full Speed USB v1.0
usbus2: 480Mbps High Speed USB v2.0
usbus3: 12Mbps Full Speed USB v1.0
ugen0.1: <Generic EHCI root HUB> at usbus0
uhub0: <Generic EHCI root HUB, class 9/0, rev 2.00/1.00, addr 1> on usbus0
ugen3.1: <Generic OHCI root HUB> at usbus3
uhub1: <Generic OHCI root HUB, class 9/0, rev 1.00/1.00, addr 1> on usbus3
ugen2.1: <Generic EHCI root HUB> at usbus2
uhub2: <Generic EHCI root HUB, class 9/0, rev 2.00/1.00, addr 1> on usbus2
ugen1.1: <Generic OHCI root HUB> at usbus1
uhub3: <Generic OHCI root HUB, class 9/0, rev 1.00/1.00, addr 1> on usbus1
mmcsd0: 8GB <SDHC SA08G 0.4 SN 9C800172 MFG 05/2010 by 2 TM> at mmc0 50.0MHz/4bit/4096-block
fbd0 on fb0
VT: initialize with new VT driver "fb".
uhub1: 1 port with 1 removable, self powered
Trying to mount root from cd9660:/dev/mmcsd0s2 []...
mmc0: Failed to set VCCQ for card at relative address 4660
Warning: no time-of-day clock registered, system time will not be set accurately
uhub3: 1 port with 1 removable, self powered
uhub0: 1 port with 1 removable, self powered
uhub2: 1 port with 1 removable, self powered
random: read_random_uio unblock wait
random: unblocking device.
lo0: link state changed to UP
/tmp: optimization changed from SPACE to TIME
emac0: link state changed to DOWN